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PCB development needs-high-density thinning

2020-01-02 11:11:21

First, the demand for copper foil:

PCBs are all developing towards high-density thin lines, HDI boards are particularly prominent. Ten years ago, the definition of IPC as HDI board was that the line width / space (L / S) was 0.1mm / 0.1mm below. Now in the industry, the conventional L / S is basically 60μm, the advanced L / S is 40 μm. Japan's 2013 installation technology roadmap data is that in 2014 HDI board conventional L / S is 50 μm, advanced L / S is 35 μm, trial L / S is 20 μm.

The PCB circuit pattern is formed by a traditional chemical etching process (subtraction method) after photoimaging on a copper foil substrate. The minimum limit for making fine lines by the subtraction method is about 30 μm, a thin copper foil (9-12 μm) substrate is required. . Due to the high price of thin copper foil CCL the lamination defects of thin copper foil, many factories produce 18μm copper foil then use etching to reduce the thickness of the copper layer. This method has many procedures, difficult thickness control, high cost. It is better to use thin copper foil. In addition, when the PCB circuit L / S is less than 20 μm, generally thin copper foil is difficult to perform, an ultra-thin copper foil (3 to 5 μm) substrate an ultra-thin copper foil attached to a carrier are required.

In addition to the thinner copper foils required for current fine circuits, the copper foils also require low roughness on the surface. Generally, in order to improve the bonding force between the copper foil the substrate ensure the peel strength of the conductor, the copper foil layer is roughened. The roughness of the conventional copper foil is greater than 5 μm. Copper foil with rough peaks embedded in the substrate improves the peel resistance, but in order to control the accuracy of the conductors during the etching of the circuit, it is easy to have the peaks of the embedded substrate remaining, which causes short circuit insulation between the circuits. The line is particularly serious. Therefore, copper foils with low roughness (less than 3 μm) are needed, copper foils with even lower roughness (1.5 μm) are needed.


Second, the demand for laminated dielectric sheets:

The technical characteristics of HDI board are the Building Up Process, the commonly used resin-coated copper foil (RCC), the laminated layer of semi-cured epoxy glass cloth copper foil is difficult to reach the fine circuit. Nowadays, the semi-additive method (SAP) modified semi-processing method (MSAP) is adopted, that is, an insulating dielectric film is laminated, then electroless copper plating is used to form a copper conductor layer. Because the copper layer is extremely thin, it is easy to form fine lines.

One of the key points of the semi-additive technology is the laminated dielectric material. In order to meet the requirements of high-density fine lines, the laminated electrical material has requirements for dielectric electrical properties, insulation, heat resistance, bonding power, adaptability to HDI board technology. At present, the international HDI laminated dielectric materials are mainly ABF / GX series products of Ajinomoto, Japan. Epoxy resin is used with different curing agents to add inorganic powder to improve the rigidity of the material reduce CTE. There are also glass fiber cloths to enhance rigidity. . In addition, there are similar thin-film laminated materials Sekisui Chemical Co. of Japan, the Taiwan Industrial Research Institute has also developed such materials. ABF materials are also constantly improving developing. The new generation of laminated materials especially requires low surface roughness, low thermal expansion rate, low dielectric loss thin rigid reinforcement.

In the global semiconductor package, the IC package carrier board replaces the ceramic substrate with an organic substrate, the pitch of the flip chip (FC) package carrier board is getting smaller smaller. Now the typical line width / space is 15 μm, it will be thinner. The performance of multi-layer carrier boards requires low dielectric properties, low thermal expansion coefficient, high heat resistance. Pursuing low-cost substrates while meeting performance goals. At present, the mass production of fine circuits basically adopts the MSPA process of insulating dielectric lamination thin copper foil. The SAP method is used to manufacture circuit patterns with L / S less than 10 μm.

When the PCB is denser thinner, the HDI board technology is developed a core-containing board to an arbitrary layer without core. Anylayer is the same function as an HDI board with any layer of interconnects. Area thickness can be reduced by about 25%. These must use thinner dielectric layers that maintain good electrical properties. Circuit board manufacturer

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